1. Field of the Invention
The present invention relates to a nonvolatile storage device, such as a flash EEPROM and, more particularly, to a high-density storage device comprising memory cells connected in series.
2. Description of the Prior Art
An EEPROM (electrically erasable and programmable ROM) such as disclosed in Japanese Patent Laid-open (Kokai) No. Hei 2-112286 can be programmed and erased repeatedly. In programming this EEPROM, the program stored in the EEPROM need not be erased by irradiation with ultraviolet light and data stored in the EEPROM can be erased or data can be written in the EEPROM by electric signals. Such read/write possibility of the EEPROM is available for memory cards.
The EEPROM will be described with reference to FIGS. 1 and 2 showing a flash EEPROM comprising NAND type basic blocks.
Cell isolating regions 54 are formed on the upper surface of a p-type silicon substrate excluding transistor forming regions 51 and 52 in which basic blocks are to be formed. Gate insulating films 55 and 56 for nonvolatile memory cells are formed in the transistor forming regions 51 and 52 on the upper surface of the silicon substrate 53 by a LOCOS process.
A floating gate forming pattern 57 is formed over the gate insulating film 55 on the part of the transistor forming region 51 and over a portion of the cell isolating region 54a. At the same time, a floating gate forming pattern 58 is formed over the gate insulating film 56 on the part of the transistor forming regions 52 and over the cell isolating region 54b.
Insulating films 59 and 60 are formed over the floating gate forming patterns 57 and 58. Gate insulating films 61 and 62 for insulating the gates of enhancement mode transistors are formed on the silicon substrate in regions between the floating gate forming pattern 57 and the cell isolating region 54a and between the floating gate forming pattern 58 and the cell isolating region 54c.
A polycrystalline silicon film is formed entirely over the floating gate forming patterns 57 and 58, and the polycrystalline silicon film is subjected to a photolithographic process and an etching process to form word lines and floating gates 63 and 64. The word lines form control gates 65 and 66 on the floating gates 63 and 64 and form transfer gates on the gate insulating films 61 and 62. In forming the control gates 65 and 66, a first selector gate 69 and a second selector gate 70 are formed.
Source-drain regions 71 and 72 of a LDD construction having a LDD diffused layer, not shown, are formed on the silicon substrate 53 on the both sides of the floating gates 63 and 64 and the transfer gates 67 and 68. Drain regions 73 and 74 are formed on the silicon substrate 53 on the opposite side of the first selector gate 69 with respect to the control gates 65 and 66, and a source region 75 is formed on the silicon substrate on the opposite side of the control gates 65 and 66 with respect to the second selector gate 70.
Interlayer insulating film 76 is formed over the control gates 65 and 66, and contact holes 77 and 78 are formed in the interlayer insulating film 76 at positions corresponding to the drain regions 73 and 74. The drain regions 73 and 74 are connected through the contact holes 77 and 78 to data lines 79 and 80.
In this EEPROM, the nonvolatile memory cells and the enhancement mode transistors are formed contiguously. Therefore, it is difficult to control the LDD dose of the source-drain region of each transistor individually and hence the respective LDD densities of the transistors are the same. Accordingly, required characteristics of write operation and erase operation are the same. Then it is difficult to realize a suitable characteristic for each operation mode.
Furthermore, if the LDD diffused layer has a normal LDD dose, which is not sufficient for the LDD diffused layer of the nonvolatile memory cell, writing is impossible. If the LDD dose of the LDD diffused layer is increased beyond a normal dose to facilitate writing, the enhancement mode transistor malfunctions due to hot electron effect.
In fabricating this conventional EEPROM, portions of the gate insulating film on the opposite sides of the transfer gate are removed in forming the control gate and the transfer gate by etching and in removing portions of the gate insulating film on the opposite sides of the control gate and the transfer gate. Consequently, portions of the silicon substrate on the opposite sides of the transfer gates are etched to form grooves in the silicon substrate on the opposite sides of the transfer gate in forming the floating gate by etching the floating gate forming pattern, and thereby the transfer gate is formed in a so-called trench gate construction. Consequently, punch through occurs across the source and the drain of the transfer transistor. Moreover, it is impossible to secure sufficient transconductance gm and sufficient load driving ability .beta. due to offset Consequently, malfunction, such as delay in write operation or erase operation, occurs.
Furthermore, a threshold voltage V.sub.thHigh after writing, a supply voltage V.sub.dd must meet an inequality: 0&lt;V.sub.thHigh &lt;V.sub.dd. Normally the supply voltage V.sub.dd is 5 V, and hence 0&lt;V.sub.thHigh &lt;5 V. Accordingly, the threshold voltage V.sub.thHigh is, taking errors into consideration, in the range of 2.+-.1 V. If the supply voltaged V.sub.dd is a low voltage on the order of 3 V, the threshold voltage V.sub.thHigh exceeds the upper limit of the voltage range for the threshold voltage V.sub.thHigh. Therefore, the threshold voltage V.sub.thHigh must be, taking errors into consideration, in the range of 1.5.+-.0.5 V, which is difficult to meet the need of the market for low-voltage operation.
Still further, if EEPROMs are fabricated for the threshold voltage V.sub.thHigh in such a narrow range, EEPROMs not meeting standards for the threshold voltage V.sub.thHigh increase to reduce the yield of the process. Thus, such EEPROMs are not suitable for mass production.